1. Field of the Invention
The present invention relates to a semiconductor device.
2. Description of the Related Art
With the recent increase in the integration of semiconductor integrated circuits, semiconductor chips having as large a number of transistors as 1,000,000,000 (1 Giga (G)), have been developed for state-of-the-art micro-processing units (MPUs). As disclosed by Hirokazu YOSHIZAWA in “Shi mosu opi anpu kairo jitsumu sekkei no kiso (Fundamentals on CMOS OP amp circuit design for practical use)”, CQ Publishing Co., Ltd., p. 23, traditional transistors formed in a planar manner, called planar transistors, require complete isolation of an n-well region that forms a p-channel metal-oxide semiconductor (PMOS) and a p-type silicon substrate (or p-well region) that forms an n-channel metal-oxide semiconductor (NMOS) from each other. In addition, the n-well region and the p-type silicon substrate require body terminals for applying potentials thereto, which will contribute to a further increase in the area of the transistors.
To address the issues described above, a surrounding gate transistor (SGT) having a structure in which a source, a gate, and a drain are arranged in a direction perpendicular to a substrate and in which the gate surrounds an island-shaped semiconductor layer has been proposed, and a method for manufacturing an SGT and a complementary metal-oxide semiconductor (CMOS) inverter, a NAND circuit, or a static random access memory (SRAM) cell which employs SGTs are disclosed. See, for example, Japanese Patent No. 5130596, Japanese Patent No. 5031809, Japanese Patent No. 4756221, and International Publication No. WO2009/096465.
FIGS. 15, 16, and 17 illustrate a circuit diagram and layout diagrams of an inverter that employs SGTs.
FIG. 15 is a circuit diagram of the inverter. The symbol Qp denotes a p-channel MOS transistor (hereinafter referred to as a “PMOS transistor”), the symbol Qn denotes an n-channel MOS transistor (hereinafter referred to as an “NMOS transistor”), the symbol IN denotes an input signal, the symbol OUT denotes an output signal, the symbol Vcc denotes a power supply, and the symbol Vss denotes a reference power supply.
FIG. 16 illustrates a plan view of the layout of the inverter illustrated in FIG. 15, which is formed by SGTs. FIG. 17 illustrates a cross-sectional view taken along the cut-line A-A′ in the plan view of FIG. 16.
In FIGS. 16 and 17, planar silicon layers 2p and 2n are formed on top of an insulating film such as a buried oxide (BOX) film layer 1 disposed on a substrate. The planar silicon layers 2p and 2n are formed as a p+ diffusion layer and an n+ diffusion layer, respectively, through impurity implantation or the like. Reference numeral 3 denotes a silicide layer disposed on surfaces of the planar silicon layers (2p and 2n). The silicide layer 3 connects the planar silicon layers 2p and 2n to each other. Reference numeral 4n denotes an n-type silicon pillar, and reference numeral 4p denotes a p-type silicon pillar. Reference numeral 5 denotes a gate insulating film that surrounds the silicon pillars 4n and 4p. Reference numeral 6 denotes a gate electrode, and reference numeral 6a denotes a gate line. A p+ diffusion layer 7p and an n+ diffusion layer 7n are formed in top portions of the silicon pillars 4n and 4p, respectively, through impurity implantation or the like. Reference numeral 8 denotes a silicon nitride film for protecting the gate insulating film 5 and the like, and reference numerals 9p and 9n denote silicide layers for connection to the p+ diffusion layer 7p and the n+ diffusion layer 7n, respectively. Reference numerals 10p and 10n denote contacts that respectively connect the silicide layers 9p and 9n to metal lines 13a and 13b. Reference numeral 11 denotes a contact that connects the gate line 6a to a metal line 13c. 
The silicon pillar 4n, the diffusion layer 2p, the diffusion layer 7p, the gate insulating film 5, and the gate electrode 6 constitute the PMOS transistor Qp. The silicon pillar 4p, the diffusion layer 2n, the diffusion layer 7n, the gate insulating film 5, and the gate electrode 6 constitute the NMOS transistor Qn. The diffusion layers 7p and 7n serve as sources, and the diffusion layers 2p and 2n serve as drains. The power supply Vcc is supplied to the metal line 13a, and the reference power supply Vss is supplied to the metal line 13b. The input signal IN is connected to the metal line 13c. The output signal OUT is output from the silicide layer 3, which connects the drain of the PMOS transistor Qp, or the diffusion layer 2p, to the drain of the NMOS transistor Qn, or the diffusion layer 2n. 
In the inverter illustrated in FIGS. 15, 16, and 17, which employs SGTs, the PMOS transistor and the NMOS transistor are structurally isolated completely from each other. This configuration eliminates the need for isolation of wells, unlike planar transistors. In addition, the silicon pillars act as floating bodies. This configuration eliminates the need for any body terminals for supplying potentials to the wells unlike planar transistors. The layout (arrangement) of the inverter is thus compact.